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Renesas LSIs Preliminary
Notice: This is not final specification. Some parametric limits are subject to change.
M5M5T5672TG - 20
18874368-BIT(262144-WORD BY 72-BIT) NETWORK SRAM
DESCRIPTION
The M5M5T5672TG is a family of 18M bit synchronous SRAMs organized as 262144-words by 72-bit. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Renesas's SRAMs are fabricated with high performance, low power CMOS technology, providing greater reliability. M5M5T5672TG operates on a single 2.5V power supply and are 2.5V CMOS compatible.
FUNCTION
Synchronous circuitry allows for precise cycle control triggered by a positive edge clock transition. Synchronous signals include : all Addresses, all Data Inputs, all Chip Enables (E1#, E2, E3#), Address Advance/Load (ADV), Byte Write Enables (BWa#, BWb#, BWc#, BWd#, BWe#, BWf#, BWg#, BWh#) and Read/Write (W#). Write operations are controlled by the eight Byte Write Enables (BWa# - BWh#) and Read/Write(W#) inputs. All writes are conducted with on-chip synchronous self-timed write circuitry. Asynchronous inputs include Output Enable (G#), Clock (CLK) and Snooze Enable (ZZ). The HIGH input of ZZ pin puts the SRAM in the power-down state. The Linear Burst order (LBO#) is DC operated pin. LBO# pin will allow the choice of either an interleaved burst, or a linear burst. All read, write and deselect cycles are initiated by the ADV Low input. Subsequent burst address can be internally generated as controlled by the ADV HIGH input.
FEATURES
* Fully registered inputs and outputs for pipelined operation * Fast clock speed: 200 MHz * Fast access time: 3.2 ns * Single 2.5V -5% and +5% power supply VDD * Individual byte write (BWa# - BWh#) controls may be tied LOW * Single Read/Write control pin (W#) * Snooze mode (ZZ) for power down * Linear or Interleaved Burst Modes * JTAG boundary scan support
APPLICATION
High-end networking products that require high bandwidth, such as switches and routers.
PACKAGE
Bump M5M5T5672TG 209(11X19) bump BGA Body Size 14mm X 22mm Bump Pitch 1mm
PART NAME TABLE
Part Name M5M5T5672TG -20 Access 3.2ns Cycle 5.0ns Active Current (max.) 450mA Standby Current (max.) 30mA
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18874368-BIT(262144-WORD BY 72-BIT) NETWORK SRAM
BUMP LAYOUT(TOP VIEW) 209 bump BGA
1 A B C D E F G H J K L M N P R T U V W DQg DQg DQg DQg DQPg DQc DQc DQc DQc NC DQh DQh DQh DQh DQPd DQd DQd DQd DQd
2 DQg DQg DQg DQg DQPc DQc DQc DQc DQc NC DQh DQh DQh DQh DQPh DQd DQd DQd DQd
3 A6 BWc# BWh# VSS VDDQ VSS VDDQ VSS VDDQ CLK VDDQ VSS VDDQ VSS VDDQ VSS NC A5 TMS
4 E2 BWg# BWd# NC VDDQ VSS VDDQ VSS VDDQ NC VDDQ VSS VDDQ VSS VDDQ NC A3 A4 TDI
5 A7 NC NC NC VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD NC NC A16 A2
6 ADV W# E1# G# VDD NC NC NC MCH CKE# MCH MCH NC ZZ VDD LBO# A15 A1 A0
7 A8 A17 NC NC VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD NC NC A13 A14
8 E3# BWb# BWe# NC VDDQ VSS VDDQ VSS VDDQ NC VDDQ VSS VDDQ VSS VDDQ NC A11 A12 TDO
9 A9 BWf# BWa# VSS VDDQ VSS VDDQ VSS VDDQ NC VDDQ VSS VDDQ VSS VDDQ VSS NC A10 TCK
10 DQb DQb DQb DQb DQPf DQf DQf DQf DQf NC DQa DQa DQa DQa DQPa DQe DQe DQe DQe
11 DQb DQb DQb DQb DQPb DQf DQf DQf DQf NC DQa DQa DQa DQa DQPe DQe DQe DQe DQe
Note1. MCH means "Must Connect High". MCH should be connected to HIGH.
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18874368-BIT(262144-WORD BY 72-BIT) NETWORK SRAM
BLOCK DIAGRAM
VDD VDDQ
A0 A1 A2~17
18 18 ADDRESS REGISTER A1 D1 A0 D0 LINEAR/ INTERLEAVED BURST COUNTER Q1 A0' Q0 A1' 16
LBO# CLK CKE#
18
WRITE ADDRESS REGISTER1
WRITE ADDRESS REGISTER2
18
ZZ ADV BWa# BWb# BWc# BWd# BWe# BWf# BWg# BWh# W#
BYTE1 WRITE DRIVERS OUTPUT REGISTERS BYTE2 WRITE DRIVERS BYTE3 WRITE DRIVERS BYTE4 WRITE DRIVERS 256Kx36 OUTPUT BUFFERS
AND DATA COHERENCY CONTROL LOGIC
MEMORY ARRAY
INPUT 72 REGISTER1
INPUT REGISTER0
G# E1# E2 E3#
READ LOGIC
VSS
Note2. The BLOCK DIAGRAM does not include the Boundary Scan logic. See Boundary Scan chapter. Note3. The BLOCK DIAGRAM illustrates simplified device operation. See TRUTH TABLE, PIN FUNCTION and timing diagrams for detailed information.
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OUTPUT SELECT
WRITE REGISTRY
DQa DQPa DQb DQPb DQc DQPc DQd DQPd DQe DQPe DQf DQPf DQg DQPg DQh DQPh
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M5M5T5672TG - 20
18874368-BIT(262144-WORD BY 72-BIT) NETWORK SRAM
PIN FUNCTION
Pin A0~A17 BWa#, BWb#, BWc#, BWd#, Bwe#, BWf#, BWg#, BWh# CLK E1# E2 E3# CKE# G# ADV ZZ Name
Synchronous Address Inputs Synchronous Byte Write Enables
Function
These inputs are registered and must meet the setup and hold times around the rising edge of CLK. A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired. These active LOW inputs allow individual bytes to be written when a WRITE cycle is active and must meet the setup and hold times around the rising edge of CLK. BYTE WRITEs need to be asserted on the same cycle as the address. BWs are associated with addresses and apply to subsequent data. BWa# controls DQa, DQPa pins; BWb# controls DQb, DQPb pins; BWc# controls DQc, DQPc pins; BWd# controls DQd, DQPd pins; BWe# controls DQe, DQPe pins; BWf# controls DQf, DQPf pins; BWg# controls DQg, DQPg pins; BWh# controls DQh, DQPh pins. This signal registers the address, data, chip enables, byte write enables and burst control inputs on its rising edge. All synchronous inputs must meet setup and hold times around the clock's rising edge. This active LOW input is used to enable the device and is sampled only when a new external address is loaded (ADV is LOW). This active HIGH input is used to enable the device and is sampled only when a new external address is loaded (ADV is LOW). This input can be used for memory depth expansion. This active LOW input is used to enable the device and is sampled only when a new external address is loaded (ADV is LOW). This input can be used for memory depth expansion. This active LOW input permits CLK to propagate throughout the device. When HIGH, the device ignores the CLK input and effectively internally extends the previous CLK cycle. This input must meet setup and hold times around the rising edge of CLK. This active LOW asynchronous input enable the data I/O output drivers. When HIGH, this input is used to advance the internal burst counter, controlling burst access after the external address is loaded. When HIGH, W# is ignored. A LOW on this pin permits a new address to be loaded at CLK rising edge. This active HIGH asynchronous input causes the device to enter a low-power standby mode in which all data in the memory array is retained. When active, all other inputs are ignored. When this pin is LOW or NC, the SRAM normally operates. This active input determines the cycle type when ADV is LOW. This is the only means for determining READs and WRITEs. READ cycles may not be converted into WRITEs (and vice versa) other than by loading a new address. A LOW on the pin permits BYTE WRITE operations and must meet the setup and hold times around the rising edge of CLK. Full bus width WRITEs occur if all byte write enables are LOW. Byte "a" is DQa , DQPa pins; Byte "b" is DQb, DQPb pins; Byte "c" is DQc, DQPc pins; Byte "d" is DQd,DQPd pins; Byte "e" is DQe, DQPe pins; Byte "f" is DQf, DQPf pins; Byte "g" is DQg, DQPg pins; Byte "h" is DQh, DQPh pins. Input data must meet setup and hold times around CLK rising edge. This DC operated pin allows the choice of either an interleaved burst or a linear burst. If this pin is HIGH or NC, an interleaved burst occurs. When this pin is LOW, a linear burst occurs, and input leak current to this pin. Core Power Supply Ground I/O buffer Power supply
Clock Input Synchronous Chip Enable Synchronous Chip Enable Synchronous Chip Enable Synchronous Clock Enable Output Enable Synchronous Address Advance/Load Snooze Enable
W#
Synchronous Read/Write
DQa,DQPa,DQb,DQPb, DQc,DQPc,DQd,DQPd, DQe,DQPe,DQf,DQPf, DQg,DQPg,DQh,DQPh LBO# VDD VSS VDDQ TDI TDO TCK TMS NC
Synchronous Data I/O Burst Mode Control VDD VSS VDDQ
Test Data Input Test Data Output Test Clock Test Mode Select No Connect
These pins are used for Boundary Scan Test.
These pins are not internally connected and may be connected to ground.
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18874368-BIT(262144-WORD BY 72-BIT) NETWORK SRAM
DC OPERATED TRUTH TABLE
Name LBO# Input Status HIGH or NC Operation Interleaved Burst Sequence
LOW Linear Burst Sequence Note4. LBO# is DC operated pin. Note5. NC means No Connection. Note6. See BURST SEQUENCE TABLE about interleaved and Linear Burst Sequence.
BURST SEQUENCE TABLE
(1) Interleaved Burst Sequence (when LBO# = HIGH or NC) Operation First access, latch external address Second access(first burst address) Third access(second burst address) Fourth access(third burst address) (2) Linear Burst Sequence (when LBO# = LOW) Operation First access, latch external address Second access(first burst address) Third access(second burst address) A17~A2 A17~A2 latched A17~A2 latched A17~A2 0,0 0,1 1,0 1,1 0,1 1,0 1,1 0,0 A1,A0 1,0 1,1 0,0 0,1 1,1 0,0 0,1 1,0 A17~A2 A17~A2 latched A17~A2 latched A17~A2 latched A17~A2 0,0 0,1 1,0 1,1 0,1 0,0 1,1 1,0 A1,A0 1,0 1,1 0,0 0,1 1,1 1,0 0,1 0,0
Fourth access(third burst address) latched A17~A2 Note7. The burst sequence wraps around to its initial state upon completion.
TRUTH TABLE
E1# E2 E3# ADV W# BWx# G# CKE# ZZ# CLK L->H L->H L->H L->H L->H L->H L->H L->H L->H L->H L->H L->H L->H Address used None None None None External Next External Next External Next None Next Current Operation
H X X X L X L X L X L X X
X L X X H X H X H X H X X
X X H X L X L X L X L X X
L L L H L H L H L H L H X
X X X X H X H X L X L X X
X X X X X X X X L L H H X
X X X X L L H H X X X X X
L L L L L L L L L L L L H
L L L L L L L L L L L L L
Deselect Cycle Deselect Cycle Deselect Cycle Continue Deselect Cycle Read Cycle, Begin Burst Read Cycle, Continue Burst NOP/Dummy Read, Begin Burst Dummy Read, Continue Burst Write Cycle, Begin Burst Write Cycle, Continue Burst NOP/Write Abort, Begin Burst Write Abort, Continue Burst Ignore Clock edge, Stall
H X None X X X X X X X X Snooze Mode Note8. "H" = input VIH; "L" = input VIL; "X" = input VIH or VIL. Note9. BWx#=H means all Synchronous Byte Write Enables (BWa#,BWb#,BWc#,BWd#) are HIGH. BWx#=L means one or more Synchronous Byte Write Enables are LOW. Note10. All inputs except OE# and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.
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18874368-BIT(262144-WORD BY 72-BIT) NETWORK SRAM
STATE DIAGRAM
F,L,X
Deselect
F,L,X
T,L,H
X,H,X
T,L,L
F,L,X
T,L,H
Read Begin Burst
T,L,L T,L,H
Write Begin Burst
T,L,L
T,L,H
X,H,X
X,H,X
T,L,L
X,H,X
Read Continue Burst
T,L,L
T,L,H
Write Continue Burst
X,H,X
Key
Input Command Code
f
Transition
Current State
Next State
Note11. The notation "x , x , x" controlling the state transitions above indicate the state of inputs E, ADV and W# respectively. Note12. If (E1# = L and E2 = H and E3# = L) then E="T" else E="F". Note13. "H" = input VIH; "L" = input VIL; "X" = input VIH or VIL; "T" = input "true"; "F" = input "false".
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18874368-BIT(262144-WORD BY 72-BIT) NETWORK SRAM
WRITE TRUTH TABLE
W# BWa# BWb# BWc# BWd# BWe# BWf# BWg# BWh#
Function Read Write Byte "a" Write Byte "b" Write Byte "c" Write Byte "d" Write Byte "e" Write Byte "f" Write Byte "g" Write Byte "h" Write All Bytes
H L L L L L L L L L
X L H H H H H H H L
X H L H H H H H H L
X H H L H H H H H L
X H H H L H H H H L
X H H H H L H H H L
X H H H H H L H H L
X H H H H H H L H L
X H H H H H H H L L
L H H H H H H H H Write Abort / NOP Note14. "H" = input VIH; "L" = input VIL; "X" = input VIH or VIL. Note15. All inputs must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.
ABSOLUTE MAXIMUM RATINGS
Symbol VDD VDDQ VI VO PD TOPR TSTG(bias) Parameter Power Supply Voltage I/O Buffer Power Supply Voltage Input Voltage Output Voltage Maximum Power Dissipation (VDD) Operating Temperature Storage Temperature(bias) With respect to VSS Conditions Ratings -1.0*~3.6 -1.0*~3.6 -1.0~VDDQ+1.0 ** -1.0~VDDQ+1.0 ** 1050 0~70 -10~85 -55~125 Unit V V V V mW C C C
TSTG Storage Temperature Note16. * This is -1.0V when pulse width2ns, and -0.5V in case of DC. ** This is -1.0V~VDDQ+1.0V when pulse width2ns, and -0.5V~VDDQ+0.5V in case of DC.
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18874368-BIT(262144-WORD BY 72-BIT) NETWORK SRAM
DC ELECTRICAL CHARACTERISTICS
Limits Symbol Parameter Power Supply Voltage I/O Buffer Power Supply Voltage High-level Input Voltage Low-level Input Voltage High-level Output Voltage Low-level Output Voltage Input Leakage Current except ZZ and LBO# Input Leakage Current of LBO# Input Leakage Current of ZZ Output Leakage Current Power Supply Current : Operating IOH = -2.0mA IOL = 2.0mA VI = 0V ~ VDDQ VI = 0V ~ VDDQ VI = 0V ~ VDDQ VI/O = 0V ~ VDDQ Condition Min Max Unit
VDD VDDQ VIH VIL VOH VOL ILI ILO ICC1
2.375 2.375 1.7 -0.3* VDDQ-0.4
2.625 2.625 VDDQ+0.3* 0.7
V V V V V
0.4 10 100 100 10 450 180 30 30 140
V
A
A mA mA mA mA mA
Device selected; Output Open, VIVIL or VIVIH, ZZVIL Device deselected ICC2 Power Supply Current : Deselected VIVIL or VIVIH, ZZVIL Device deselected; Output Open CMOS Standby Current VIVSS+0.2V or VIVDDQ-0.2V ICC3 (CLK stopped standby mode) CLK frequency=0Hz, All inputs static Snooze mode Snooze Mode Standby Current ICC4 ZZVDDQ-0.2V, LBO#VDD-0.2V Device selected; Stall Current Output Open, CKE#VIH ICC5 VIVSS+0.2V or VIVDDQ-0.2V Note17.*VILmin is -1.0V and VIH max is VDDQ+1.0V in case of AC(Pulse width2ns). Note18."Device Deselected" means device is in power-down mode as defined in the truth table.
CAPACITANCE
Symbol CI Parameter Input Capacitance Condition
VI=GND, VI=25mVrms, f=1MHz VO=GND, VO=25mVrms, f=1MHz
Limits Min Typ Max 6 8
Unit pF pF
CO Input / Output (DQ) Capacitance Note19. This parameter is sampled.
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18874368-BIT(262144-WORD BY 72-BIT) NETWORK SRAM
THERMAL RESISTANCE 4-Layer PC board mounted (70x70x1.6mmT)
Symbol JA JC Parameter Thermal resistance Junction Ambient Thermal resistance Junction to Case Condition Air velocity=0m/sec Air velocity=2m/sec Limits Min Typ 26 18 6 Max Unit C/W C/W C/W
AC ELECTRICAL CHARACTERISTICS (Ta=0~70C, VDD=VDDQ=2.375~2.625V, unless otherwise noted) (1) MEASUREMENT CONDITION
Input pulse levels **************************************** VIH=VDDQ, VIL=0V Input rise and fall times ******************************* faster than or equal to 1V/ns Input timing reference levels *********************** VIH=VIL=VDDQ / 2 Output reference levels ******************************* VIH=VIL=VDDQ / 2 Output load ************************************************** Fig.1
Q ZO=50
30pF (Including wiring and JIG) 50 VT=VDDQ / 2 Fig.1 Output load
Input Waveform Output Waveform
VDDQ / 2 tplh VDDQ / 2 tphl
Input Waveform toff Vh Output Waveform (toff) Vl
VDDQ / 2 ton (ton)
Vh-(0.2(Vh-Vz)) Vz+(0.2(Vh-Vz)) Vz 0.2(Vz-Vl) Vz-(0.2(Vz-Vl))
Fig.2 Tdly measurement
Fig.3 Tri-State measurement
Note20.Valid Delay Measurement is made from the VDDQ/2 on the input waveform to the VDDQ/2 on the output waveform. Input waveform should have a slew rate of faster than or equal to 1V/ns. Note21.Tri-state toff measurement is made from the VDDQ/2 on the input waveform to the output waveform moving 20% from its initial to final Value VDDQ/2. Note:the initial value is not VOL or VOH as specified in DC ELECTRICAL CHARACTERISTICS table. Note22. Tri-state ton measurement is made from the VDDQ/2 on the input waveform to the output waveform moving 20% from its initial Value VDDQ/2 to its final Value. Note:the final value is not VOL or VOH as specified in DC ELECTRICAL CHARACTERISTICS table. Note23.Clocks,Data,Address and control signals will be tested with a minimum input slew rate of faster than or equal to 1V/ns.
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18874368-BIT(262144-WORD BY 72-BIT) NETWORK SRAM
(2)TIMING CHARACTERISTICS
Limits 200MHz -20 Min Max 5.0 2.0 2.0 3.2 1.5 1.5 1.5 0.0 3.2 1.0 1.0 1.0 1.0 1.0 1.0 0.8 0.8 0.8 0.8 0.8 0.8 2*tKHKH 2*tKHKH
Symbol
Parameter
Unit
Clock tKHKH Clock Cycle Time tKHKL Clock HIGH Time tKLKH Clock LOW Time Output times tKHQV Clock HIGH to Output Valid tKHQX Clock HIGH to Output Invalid tKHQX1 Clock HIGH to Output in Low-Z tKHQZ Clock HIGH to Output in High-Z tGLQV G# to output valid tGLQX1 G# to output in Low-Z G# to output in High-Z tGHQZ Setup Times Address Valid to Clock HIGH tAVKH tadvVKH ADV Valid to Clock HIGH tWVKH Write Valid to Clock HIGH tBxVKH Byte Write Valid to Clock HIGH (BWa#~BWh#) tEVKH Enable Valid to Clock HIGH (E1#,E2,E3#) tDVKH Data In Valid Clock HIGH Hold Times tKHAX Clock HIGH to Address don't care tKHadvX Clock HIGH to ADV don't care tKHWX Clock HIGH to Write don't care tKHBxX Clock HIGH to Byte Write don't care (BWa#~BWh#) tKHEX Clock HIGH to Enable don't care (E1#,E2,E3#) tKHDX Clock HIGH to Data In don't care ZZ tZZS ZZ standby tZZREC ZZ recovery
Note24.All parameter except tZZS, tZZREC in this table are measured on condition that ZZ=LOW fix. Note25.Test conditions is specified with the output loading shown in Fig.1 unless otherwise noted. Note26. tKHQX1, tKHQZ, tGLQX1, tGHQZ are sampled. Note27.LBO# is static and must not change during normal operation.
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
3.2 3.2
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18874368-BIT(262144-WORD BY 72-BIT) NETWORK SRAM
(3)READ TIMING
tKHKH
CLK
tKHKL tckeVKH tKHckeX tKLKH
CKE#
tEVKH tKHEX
E#
tadvVKH tKHadvX
ADV
tWVKH tKHWX
W#
BWx#
tAVKH tKHAX
A1 A2 A3
ADD
tKHQX1
tGLQV
Q(A1) Q(A2) Q(A2+1) Q(A2+2) Q(A2+3) Q(A2) Q(A3) Q(A3+1)
DQ
tKHQV
tKHQX
tGHQZ tGLQX1
tKHQZ
G#
Read A1 Read A2 Burst Read A2+1 Stall Burst Read Burst Read Burst Read A2+2 A2+3 A2 Deselect Continue Deselect Read A3 Burst Read Burst Read Burst Read A3+1 A3+2 A3+3
DON'T CARE
UNDEFINED
Note28.Q(An) refers to output from address An. Q(An+1) refers to output from the next internal burst address following An. Note29. E# represents three signals. When E# is LOW, it represents E1# is LOW, E2 is HIGH and E3# is LOW. Note30.ZZ is fixed LOW.
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(4)WRITE TIMING
tKHKH
CLK
tKHKL tckeVKH tKHckeX tKLKH
CKE#
tEVKH tKHEX
E#
tadvVKH tKHadvX
ADV
tWVKH tKHWX
W#
tBVKH tKHBX
BWx#
tAVKH tKHAX
A1 A2 A3 A4
ADD
tDVKH tKHDX
DQ
D(A1)
D(A2)
D(A2+1)
D(A2+3)
D(A2)
D(A3)
D(A4)
D(A4+1)
G#
Write A1 Write A2 Burst Write A2+1 NOP Burst Write A2+3 Write A2 Write A3 NOP Write A4 Burst Write A4+1 Stall Burst Write Burst Write A4+2 A4+3
DON'T CARE
UNDEFINED
Note31.Q(An) refers to output from address An. Q(An+1) refers to output from the next internal burst address following An. Note32. E# represents three signals. When E# is LOW, it represents E1# is LOW, E2 is HIGH and E3# is LOW. Note33.ZZ is fixed LOW.
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(5)READ/WRITE TIMING
tKHKH
CLK
tKHKL tckeVKH tKHckeX tKLKH
CKE#
tEVKH tKHEX
E#
tadvVKH tKHadvX
ADV
tWVKH tKHWX
W#
tBVKH tKHBX
BWx#
tAVKH tKHAX
A1 A2 A2 A3 A3 A4 A5
ADD
tKHQX1
tDVKH tKHDX
Q(A1) D(A2) Q(A2) D(A3) D(A3+1) Q(A3) Q(A3+1) D(A4) Q(A5)
DQ
tKHQV
tKHQV
G#
Read A1 Write A2 Read A2 Write A3 Burst Write A3+1 Read A3 Burst Read A3+1 Deselect Write A4 Stall Read A5 Burst Read Burst Read A5+1 A5+2
DON'T CARE
UNDEFINED
Note34.Q(An) refers to output from address An. Q(An+1) refers to output from the next internal burst address following An. Note35. E# represents three signals. When E# is LOW, it represents E1# is LOW, E2 is HIGH and E3# is LOW. Note36.ZZ is fixed LOW.
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(6)SNOOZE MODE TIMING
CLK
tZZS tZZREC
ZZ
All Inputs (except ZZ)
DESELECT or READ only
Q
Snooze Mode
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18874368-BIT(262144-WORD BY 72-BIT) NETWORK SRAM
JTAG PORT OPERATION Overview
The JTAG Port on this SRAM operates in a manner consistent with IEEE Standard 1149.1-1990, a serial boundary scan interface standard (commonly referred to as JTAG), but dose not implement all of the function required for 1149.1 compliance. Unlike JTAG implementations that have been common among SRAM vendors for the last several years, this implementation dose offer a form of EXTEST, known as Clock Assisted EXTEST, reducing or eliminating the "hand coding" that has been required to overcome the test program compiler errors caused by previous non-compliant implementation. The JTAG Port interfaces with conventional CMOS logic level signaling.
Disabling the JTAG port
It is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless clocked. To assure normal operation of the SRAM with the JTAG Port unused, the TCK, TDI and TMS pins may be left floating or tied to High. The TDO pin should be left unconnected.
JTAG Pin Description
Pin TCK TMS TDI Name Test Clock Test Mode Select Test Data In Function The TCK input is clock for all TAP events. All inputs are captured on the rising edge of TCK and the Test Data Out (TDO) propagates from the falling edge of TCK. The TMS input is sampled on the rising edge of TCK. This is the command input for the TAP Controller state machine. An undriven TMS input will produce the same result as a logic one input level. The TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers placed between the TDI and TDO pins. the register placed between the TDI and TDO pins is determined by the state of the TAP Controller state machine and the instruction that is currently loaded in the TAP Instruction Resister (refer to the TAP Controller State Diagram). An undriven TDI Input will produce the same result as a logic one input level. The TDO output is active depending on the state of the TAP Controller state machine. Output changes in response to the falling edge of TCK. This is the output side of the serial registers placed between the TDI and TDO pins.
TDO
Test Data Out
Note: This device dose not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1. The Test-Logic-Reset state is entered while TMS is held high for five rising edges of TCK. The TAP Controller is also reset automatically at power-up.
JTAG Port Registers
Overview The various JTAG registers, referred to as Test Access Port or TAP Registers, are selected (one at a time) via the sequence of 1s and 0s applied to TMS as TCK is strobed. Each of TAP Registers are serial shift registers that capture serial input data on the rising edge of TCK and push serial data out on the next falling edge of TCK. When a register is selected, it is placed between the TDI and TDO pins. Instruction Register The Instruction Register holds the instructions that are executed by the TAP Controller when it is moved into the Run-Test/Idle, or the various data register states. Instructions are 3 bits long. The Instruction Resister can be loaded when it is placed between the TDI and TDO pins. The Instruction Resister is automatically preloaded with the IDCODE instruction at power-up or whenever the controller is placed in the Test-Logic-Reset state.
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18874368-BIT(262144-WORD BY 72-BIT) NETWORK SRAM Bypass Register The Bypass resister is a single-bit register that can be placed between the TDI and TDO pins. It allows serial test data to be passed through the SRAM's JTAG Port to another device in the scan chain with as little delay as possible. Boundary Scan Register The Boundary Scan Register is a collection of flip flops that can be preset by the logic level found on the SRAM's input or I/O pins. The flip flops are then daisy chained together so the levels found can be shifted serially out of the JTAG Port's TDO pins. The Boundary Scan Register also includes a number of place holder flip flops (always set to a logic 1). The relationship between the device pins and the bits in the Boundary Scan Register is described in the Scan Order Table following. The Boundary Scan Register, under the control of the TAP Controller, is loaded with the contents of the SRAM's I/O ring when the controller is in the Capture-RD state and then is placed between the TDI and TDO pins when the controller is moved to the Shift-DR state. SAMPLE-Z, SAMPLE/PRELOAD and EXTEST instruction can be used to activate the Boundary Scan Register. Identification (ID) Register The ID register is a 32-bit register that is loaded with a device and vender specific 32-bit code when the controllers put in the Capture-DR state with the IDCODE Instruction loaded in the Instruction Register. The code is loaded from 32-bit on-chip ROM. It describes various attributes of the SRAM (see page 25). The register is then placed between the TDI and TDO pins when the controller is moved into the Shift-DR state. Bit 0 in the register is the LSB and the first to reach the TDO pin when shifting begins.
TAP Controller Instruction Set
Overview There are two classes of instructions defined in the Standard 1149.1-1990; standard (Public) instructions, and device specific (Private) instructions. Some Public instructions are mandatory for 1149.1 compliance. Optional Public instructions must be implemented in prescribed ways. Although the TAP Controller in this device follows the 1149.1 conventions, it is not 1194.1-compliant because one of the mandatory instructions, EXTEST, is uniquely implemented. The TAP on this device may be used to monitor all input and I/O pads. This device will not perform INTEST but can perform the preload portion of the SAMPLE/PRELOAD command. When the TAP controller is placed in the Capture-IR state, the two least significant bits of the instruction register are loaded with 01. When the TAP controller is moved to the Shift-IR state, the Instruction Register is placed between the TDI and TDO pins. In this state the desired instruction is serially loaded through the TDI input (while the previous contents are shifted out at the TDO output). For all instructions, the TAP executes newly loaded instructions only when the controller is moved to the Update-IR state. The TAP Instruction Set for this device is listed in the following table. Instruction Descriptions BYPASS When the BYPASS instruction is loaded in the Instruction Register, the Bypass Register is placed between the TDI and TDO pins. This occurs when the TAP Controller is moved to the Shift-DR state. This allows the board level scan path to be shortened to facilitate testing of other devices in the scan path. SAMPLE/PRELOAD SAMPLE/PRELOAD is a Standard1149.1 mandatory public instruction. When the SAMPLE/PRELOAD instruction is loaded in the Instruction Register, moving the TAP Controller into the Capture-DR state loads the data in the SRAM's input and I/O buffers into the Boundary Scan Register. Some Boundary Scan Register locations are not associated with an input or I/O pin, and are loaded with the default state identified in the BSDL file. Because the SRAM clock is independent from the TAP Clock (TCK) it is possible for the TAP to attempt to capture the I/O ring contents while the input buffers are in transition (i.e. in a metastable state). Although allowing the TAP to sample metastable inputs will not harm the device, repeatable results cannot be expected. SRAM input signals must be stabilized for long enough to meet the TAP's input data capture set-up plus hold time (tTS plus tTH). The SRAM's clock inputs need not be paused for any other TAP operation except capturing the I/O ring contents into the Boundary Scan Register. Moving the controller to the Shift-DR state then places the Boundary Scan Register between the TDI and TDO pins. 16/24 Preliminary M5M5T5672TG-20 REV.1.0
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18874368-BIT(262144-WORD BY 72-BIT) NETWORK SRAM EXTEST EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the Instruction Register is loaded with all logic 0s. EXTEST is not implemented in the TAP Controller, and therefore this device is not compliant to the 1149.1 Standard. When the EXTEST instruction is loaded into the Instruction Register, the device responds as if the SAMPLE/PRELOAD instruction has been loaded. There is one difference between the two instructions. Unlike the SAMPLE/PRELOAD instruction, EXTEST place the SRAM outputs in a High-Z state. IDCODE The IDCODE instruction cause the ID ROM to be loaded into the ID register when the controller is in the Capture-DR state and places the ID Register between the TDI and TDO pins in the Shift-DR state. The IDCODE instruction is the default instruction loaded in at power-up and any time the controller is placed in the Test-Logic-Reset state. SAMPLE-Z If the SAMPLE-Z instruction is loaded in the Instruction Register, all SRAM outputs are forced to an inactive drive state (High-Z) and the Boundary Scan Register is placed between the TDI and TDO pins when the TAP Controller is moved to the Shift-DR state. RFU These instructions are reserved for future use. Do not use these instructions.
JTAG TAP BLOCK DIAGRAM
Bypass Register 0 Instruction Register 210 TDI Identification Register 31 30 29 . . . . . . . . 2 1 0 Boundary Scan Register .. .............. .. 2 1 0 TDO
TMS TCK Test Access Port (TAP) Controller
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BOUNDARY SCAN ORDER Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 Bump 5V 6U 8U 7V 7W 8V 9V 10W 10V 10U 11W 11V 11U 11T 10T 11R 10R 11P 10P 11N 10N 11M 10M 11L 10L 6P 6J 10J 11J 10H 11H 10G 11G 10F 10E 11F 11E 10D 11D 11C Pin Name A16 A15 A11 A13 A14 A12 A10 DQe DQe DQe DQe DQe DQe DQe DQe DQPe DQPa DQa DQa DQa DQa DQa DQa DQa DQa ZZ MCH DQf DQf DQf DQf DQf DQf DQf DQPf DQf DQPb DQb DQb DQb Bit 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 Bump 11B 11A 10C 10B 10A 9A 7A 7B 8C 9C 9B 8B 6A 6D 6K 6B 3K 8A 4B 3B 3C 4C 4A 6C 5A 3A 2A 2B 2C 1A 1B 1C 1D 2D 1E 1F 2E 2F 1G 2G Pin Name DQb DQb DQb DQb DQb A9 A8 A17 BWe# BWa# BWf# BWb# ADV G# CKE# W# CLK E3# BWg# BWc# BWh# BWd# E2 E1# A7 A6 DQg DQg DQg DQg DQg DQg DQg DQg DQPg DQc DQPc DQc DQc DQc Bit 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 Bump 1H 2H 1J 2J 6L 6M 2L 1L 2M 1M 2N 1N 2P 1P 2R 1R 2T 1T 1U 1V 1W 2U 2V 2W 6T 3V 4V 4U 5W 6V 6W Pin Name DQc DQc DQc DQc MCH MCH DQh DQh DQh DQh DQh DQh DQh DQh DQPh DQPd DQd DQd DQd DQd DQd DQd DQd DQd LBO# A5 A4 A3 A2 A1 A0
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JTAG TAP CONTROLLER STATE DIAGRAM
Test-Logic-Reset 1 0 Run-Test/Idle 0 1 1 Select-DR-Scan 0 Capture-DR 0 Shift-DR 1 1 Exit1-DR 0 Pause-DR 1 Exit2-DR 1 Update-DR 1 0 0 0 1 1 1 Select-IR-Scan 0 Capture-IR 0 Shift-IR 1 Exit1-IR 0 Pause-IR 1 Exit2-IR 1 Update-IR 1 0 0 0 1
0
0
TAP CONTROLLER DC ELECTRICAL CHARACTERISTICS (Ta=0~70C, VDD=2.375~2.625V, unless otherwise noted)
Limits Min Max Test Port Input High Voltage 1.7 VDDQ+0.3 ** VIHT VILT Test Port Input Low Voltage -0.3 ** 0.7 VOHT Test Port Output High Voltage IOH=-100A VDDQ-0.1 VOLT Test Port Output Low Voltage IOL=+100A 0.1 IINT TMS, TCK and TDI Input Leakage Current -10 10 IOLT TDO Output Leakage Current Output Disable, VOUT=0V~VDDQ -10 10 Note37. **Input Undershoot/Overshoot voltage must be -1.0V19/24 Preliminary M5M5T5672TG-20 REV.1.0
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TAP CONTROLLER AC ELECTRICAL CHARACTERISTICS (Ta=0~70C, VDD=2.375~2.625V, unless otherwise noted) (1)MEASUREMENT CONDITION Input pulse levels **************************************** VIH=VDDQ, VIL=0V Input rise and fall times ******************************* faster than or equal to 1V/ns Input timing reference levels *********************** VIH=VIL=VDDQ / 2 Output reference levels *******************************VIH=VIL=VDDQ / 2 Output load ************************************************** Fig.4
Q ZO=50 50 VT=VDDQ / 2 Fig.4 Output load 30pF (Including wiring and JIG)
(2)TIMING CHARACTERISTICS
Symbol Parameter TCK Frequency TCK Cycle Time TCK High Pulse Width TCK Low Pulse Width TDI, TMS setup time TDI, TMS hold time TCK Low to TDO valid Limits Min Max 20 50 20 20 10 10 20 Unit MHz ns ns ns ns ns ns
tTF tTKC tTKH tTKL tTS tTH tTKQ
(3) TIMING
tTKC tTKH tTKL
TCK
tTS tTH
TMS
tTS tTH
TDI
tTKQ
TDO
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JTAG TAP INSTRUCTION SET SUMMARY
Instruction EXTEST IDCODE SAMPLE-Z RFU SAMPLE/PRELOAD RFU RFU BYPASS Code 000 001 010 011 100 101 110 111 Description Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO. Forces all SRAM outputs to High-Z state. This instruction is not 1149.1-compliant. Preloads ID Register and places it between TDI and TDO Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO. Forces all Data and Clock output drivers to High-Z Do not use this instruction; Reserved for Future Use. Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO. Do not use this instruction; Reserved for Future Use. Do not use this instruction; Reserved for Future Use. Places the BYPASS Register between TDI and TDO.
STRUCTURE OF IDENTIFICATION REGISTER
Revision Bit No.
M5M5T5672
31 30 29 28 27 26 25 24 23
Device Information
22 21 20 19 18 17 16 15 14 13 12 11
JEDEC Vendor Code of RENESAS
10 9 8 7 6 5 4 3 2 1 0
0
MSB
0
0
0
0
1
0
0
1
0
1
0
1
0
0
1
0
1
0
0
0
1
0
0
0
1
0
0
0
1
1
1
LSB
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PACKAGE OUTLINE 209(11x19) bump Ball Grid Array(BGA) Pin Pitch 1.0mm
Refer to JEDEC Standard MS-028, Variation BC, which can be seen at: http://www.jedec.org/download/search/MS-028C.pdf
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REVISION HISTORY Rev.No. 0.0 History First revision DC ELECTRICAL CHARACTERISTICS Changed ILI limit from 10uA to 100uA (Input Leakage Current of ZZ and LBO#) Changed Icc3 and Icc4 limit from 20mA to 30mA (Standby Current) Fixed PART NAME TABLE AC ELECTRICAL CHARACTERISTICS (2)TIMING CHARACTERISTICS Changed tKHKL limit from 1.8ns to 2.0ns. Changed tKLKH limit from 1.8ns to 2.0ns. Changed all Setup times from 1.2ns to 1.0ns. Changed all Hold times from 0.5ns to 0.8ns. 1.0 STRUCTURE OF IDENTIFICATION REGISTER Fixed JEDEC Vender Code as follows.
The semiconductor operations of HITACHI and MITSUBISHI Electric were transferred to RENESAS Technology Corporation on April 1st 2003. Both RENESAS and MITSUBISHI JEDEC vendor code are as follows
Bit No. RENESAS MITSUBISHI 11 0 0 10 1 0 9 0 0 8 0 0 7 0 0 6 1 0 5 0 1 4 0 1 3 0 1 2 1 0 1 1 0
Date September
25, 2002
Preliminary
0.1
January 31, 2003
Preliminary
August 1, 2003
Preliminary
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Nippon Bldg.,6-2,Oteamchi 2-chome,Chiyoda-ku,Tokyo,100-0004 Japan
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* Renesas Technology Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage.Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
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REJ03C0072 (c) 2003 Renesas Technology Corp. New publication, effective August 2003. Specifications subject to change without notice.

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